RISC-V is an Instruction Set Architecture (ISA) that is both free and open. This means that the RISC-V ISA itself does not require a licensing fee, although individual implementations may do so. The RISC-V ISA is curated by a non-profit foundation with no commercial interest in products or services that use it, and it is possible for anyone to submit contributions to the RISC-V specifications. The RISC-V ISA is suitable for applications ranging from embedded microcontrollers to supercomputers. This book will first describe the 32-bit RISC-V ISA, including both the base instruction set as well as the majority of the currently-defined extensions. The book will then describe, in detail, an open-source implementation of the ISA that is intended for embedded control applications. This implementation includes the base instruction set as well as a number of standard extensions. After the description of the CPU design is complete the design is expanded to include memory and some simple I/O. The resulting microcontroller will then be implemented in an affordable FPGA development board (available from Elektor) along with a simple software application so that the reader can investigate the finished design.

Monte Dalrymple BSEE (Hons.), MSEE, started his career at Zilog, where he designed several successful products, including the SCC and USC families. He was also the architect and lead designer of the Z380 microprocessor. Monte started his own company, Systemyde International Corp., in 1995, and has been doing contract design work ever since. He designed all five generations of Rabbit microprocessors, a Z180 clone, and a Z8000 clone. Monte holds 17 patents as well as both amateur and commercial radio licenses.